74AUP2G14GW

NXP  74AUP2G14GW  非门, AUP系列, 施密特触发, 1输入, 4 mA, 800mV至3.6V, SOT-363-6

The is a low-power dual Schmitt-trigger inverter provides two inverting buffer with Schmitt-trigger action which accept standard input signals. The device is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 to 3.6V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH.

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High noise immunity

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ESD Protection - HBM JESD22-A114F >5000V, MM JESD22-A115-A >200V, CDM JESD22-C101E >1000V

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0.9µA Low static power consumption ICC

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Latch-up performance exceeds 100mA per JESD 78 Class II

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Inputs accept voltages up to 3.6V

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<10% of VCC Low noise overshoot and undershoot

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IOFF circuitry provides partial power-down mode operation