74AHCT574PW,118

NXP  74AHCT574PW,118  触发器, 三态非反相, 正沿, D, 115 MHz, 25 mA, TSSOP, 20 引脚

The 74AHCT574PW is an octal positive edge-trigger D-type Flip-flop with 3-state output and high-speed Si-gate CMOS technology. It is pin compatible with low power Schottky TTL LSTTL. It features separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock and an output enable OE\\ input are common to all flip-flops. The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the low-to-high CP transition. When OE\ is low the contents of the 8 flip-flops are available at the outputs. When OE\ is high, the outputs go to the high-impedance OFF-state. Operation of the OE\ input does not affect the state of the flip-flops.

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Balanced propagation delays

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All inputs have Schmitt-trigger action

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Independent register and 3-state buffer operation

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Common 3-state output enable input

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TTL Input level

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Complies with JEDEC standard No. 7A