74HC573PW,118

NXP  74HC573PW,118  芯片, D型锁存器, 透明, 八路, TSSOP-20

The 74HC573PW is an octal transparent D Latch pin compatible with low-power Schottky TTL LSTTL. It features separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A LE input and an OE\ input are common to all latches. When LE is high, data at the Dn inputs enter the latches. In this condition, the latch is transparent, i.e. a latch output changes state each time its corresponding D input changes. When LE is low the latches store the information that was present at the D-inputs a set-up time preceding the high-to-low transition of LE. When OE\ is low, the contents of the 8 latches are available at the outputs. When OE\ is high, the outputs go to the high-impedance OFF-state. Operation of the OE\ input does not affect the state of the latch.

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Inputs and outputs on opposite sides of package allowing easy interface with microprocessors

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Useful as input or output port for microprocessors and microcomputers

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3-state Non-inverting outputs for bus-oriented applications

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Common 3-state output enable input

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CMOS Input level

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Complies with JEDEC standard No. 7A