5SGXEB9R3H43I3N

FPGA Stratix V GX Family 840000 Cells 28nm Technology 0.85V 1760Pin HFBGA

* 0.85V or 0.9V core voltage * 28.05-Gbps transceivers on Stratix V GT devices * Electronic dispersion compensation EDC for XFP, SFP+, QSFP, CFP optical module support * Adaptive linear and decision feedback equalization * Transmitter pre-emphasis and de-emphasis * Dynamic reconfiguration of individual channels * On-chip instrumentation EyeQ non-intrusive data eye monitoring * 600-Megabits per second Mbps to 12.5-Gbps data rate capability * 1.6-Gbps LVDS * 1,066-MHz external memory interface * On-chip termination OCT * 1.2V to 3.3V interfacing for all Stratix V devices * PCIe Gen3, Gen2, and Gen1 complete protocol stack, x1/x2/x4/x8 end point and root port * Interlaken physical coding sublayer PCS * Gigabit Ethernet GbE and XAUI PCS * 10G Ethernet PCS * Serial RapidIO® SRIO PCS * Common Public Radio Interface CPRI PCS * Gigabit Passive Optical Networking GPON PCS * Programmable Power Technology * Quartus II integrated PowerPlay Power Analysis * Enhanced ALM with four registers * Improved routing architecture reduces congestion and improves compile times * M20K: 20-Kbit with hard error correction code ECC * MLAB: 640-bit * Up to 600 MHz performance * Natively support signal processing with precision ranging from 9x9 up to 54x54 * New native 27x27 multiply mode * 64-bit accumulator and cascade for systolic finite impulse responses FIRs * Embedded internal coefficient memory * Pre-adder/subtractor improves efficiency * Increased number of outputs allows more independent multipliers * Fractional mode with third-order delta-sigma modulation * Integer mode * Precision clock synthesis, clock delay compensation, and zero delay buffer ZDB * 800-MHz fabric clocking * Global, quadrant, and peripheral clock networks * Unused clock networks can be powered down to reduce dynamic power * Serial and parallel flash interface * Enhanced advanced encryption standard AES design security features * Tamper protection * Partial and dynamic reconfiguration * Configuration via Protocol CvP * Multiple device densities with identical package footprints enables seamless migration between different FPGA densities * FBGA packaging with on-package decoupling capacitors * 14.1 Gbps transceivers