MC74VHC74

双D型触发器具有​​置位和复位 Dual D−Type Flip−Flop with Set and Reset

The is an advanced high speed CMOS D-type flip-flop fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The signal level applied to the D input is transferred to Q output during the positive going transition of the Clock pulse. Reset RD and Set SD are independent of the Clock CP and are accomplished by setting the appropriate input Low. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems.

Features

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High Speed: fmax = 170MHz Typ at VCC = 5V

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Low Power Dissipation: ICC = 2µA Max at TA = 25 C

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High Noise Immunity: VNIH = VNIL = 28% VCC

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Power Down Protection Provided on Inputs

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Balanced Propagation Delays

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Designed for 2V to 5.5V Operating Range

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Low Noise: VOLP = 0.8V Max

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Pin and Function Compatible with Other Standard Logic Families

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Latchup Performance Exceeds 300mA

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ESD Performance: HBM > 2000V; Machine Model > 200V

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Chip Complexity: 128 FETs or 32 Equivalent Gates

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Pb-Free Packages are Available