UPD720102GC-YEB-A

接口, USB, USB主控制器, USB 2.0, 3.135 V, 3.465 V, TQFP, 120 引脚

* Compliant with universal serial bus specification revision 2.0 data rate: 1.5/12/480 Mbps * Compliant with open host controller interface specification for USB release 1.0a * Compliant with enhanced host controller interface specification for USB revision 1.0 * PCI multi-function device consists of one OHCI host controller core for full-/low-speed signaling and one EHCI host * controller core for high-speed signaling * Root hub with 3 Max. downstream facing ports which are shared by OHCI and EHCI host controller cores * All downstream facing ports can handle high-speed 480 Mbps, full-speed 12 Mbps, and low-speed 1.5 Mbps * transaction * Supports hyper-speed transfer mode using HSMODE signal * 32-bit 33 MHz host interface compliant with PCI specification revision 2.2 * Supports PCI mobile design guide version 1.1 * Supports PCI-bus power management interface specification revision 1.1 * PCI bus bus-master access * Supports 3.3 V PCI * System clock is generated by 30 MHz crystal or 48 MHz clock input * Operational registers direct-mapped to PCI memory space * 3.3 V single power supply, 1.5 V internal operating voltage from on chip regulator * On chip Rs and Rpd resistors for USB signals