TMS320LC549GGU-80

定点数字信号处理器 FIXED-POINT DIGITAL SIGNAL PROCESSOR

description

The TMS320LC549 fixed-point, digital signal processor DSP hereafter referred to as the ’549 is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. The processor also provides an arithmetic logic unit ALU that has a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The ’549 also utilizes a highly specialized instruction set, which is the basis of its operational flexibility and speed.

• Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus

• 40-Bit Arithmetic Logic Unit ALU Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators

• 17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate MAC Operation

• Compare, Select, and Store Unit CSSU for the Add/Compare Selection of the Viterbi Operator

• Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle

• Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units ARAUs

• Data Bus With a Bus Holder Feature

• Address Bus With a Bus Holder Feature

• Extended Addressing Mode for 8M × 16-Bit Maximum Addressable External Program Space

• 192K × 16-Bit Maximum Addressable Memory Space 64K Words Program, 64K Words Data, and 64K Words I/O

• On-Chip ROM with Some Configurable to Program/Data Memory

• Dual-Access On-Chip RAM

• Single-Access On-Chip RAM

• Single-Instruction Repeat and Block-Repeat Operations for Program Code

• Block-Memory-Move Instructions for Better Program and Data Management

• Instructions With a 32-Bit Long Word Operand

• Instructions With Two- or Three-Operand Reads

• Arithmetic Instructions With Parallel Store and Parallel Load

• Conditional Store Instructions

• Fast Return From Interrupt

• On-Chip Peripherals

   − Software-Programmable Wait-State Generator and Programmable Bank Switching

   − On-Chip Phase-Locked Loop PLL Clock Generator With Internal Oscillator or External Clock Source

   − Time-Division Multiplexed TDM Serial Port

   − Buffered Serial Port BSP

   − 8-Bit Parallel Host-Port Interface HPI

   − One 16-Bit Timer

   − External-Input/Output XIO Off Control to Disable the External Data Bus, Address Bus and Control Signals

• Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes

• CLKOUT Off Control to Disable CLKOUT

• On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1† JTAG Boundary Scan Logic

• 15-ns Single-Cycle Fixed-Point Instruction Execution Time 66 MIPS for 3.3-V Power Supply

• 12.5-ns Single-Cycle Fixed-Point Instruction Execution Time 80 MIPS for 3.3-V Power Supply