SPC564A70L7COBY

PowerPC系列 120MHz 2MB 128KB

This microcontroller is a 32-bit system-on-chip SoC device intended for use in mid-range engine control and automotive transmission control applications.

It is compatible with devices in ST"s SPC56xx family and offers performance and capability above that of the SPC563M devices.

The microcontroller"s e200z4 host processor core is built on the Power Architecture technology and designed specifically for embedded applications. In addition to the Power Architecture technology, this core supports instructions for digital signal processing DSP.

The device has two levels of memory hierarchy consisting of 8 KB of instruction cache, backed by a 128 KB on-chip SRAM and a 2 MB internal flash memory.

For development, the device includes a calibration bus that is accessible only when using the STMicroelectronics calibration tool.

**Key Features**

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150 MHz e200z4 Power Architecture® core

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Variable length instruction encoding VLE

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Superscalar architecture with 2 execution units

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Up to 2 integer or floating point instructions per cycle

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Up to 4 multiply and accumulate operations per cycle

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Memory organization

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2 MB on-chip flash memory with ECC and read-while-write RWW

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128 KB on-chip SRAM with standby functionality 32 KB and ECC

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8 KB instruction cache with line locking, configurable as 2- or 4-way

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14 + 3 KB eTPU code and data RAM

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4 x 4 crossbar switch XBAR

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24-entry MMU

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Fail Safe Protection

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16-entry Memory Protection Unit MPU

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CRC unit with 3 submodules

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Junction temperature sensor

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Interrupt

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Configurable interrupt controller INTC with non-maskable interrupt NMI

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64-channel eDMA

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Serial channels

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3 eSCI modules

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3 DSPI modules 2 of which support downstream Micro Second Channel [MSC]

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3 FlexCAN modules with 64 message buffers each

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1 FlexRay module V2.1 up to 10 Mbit/s w/dual or single channel, 128 message objects, ECC

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1 eMIOS 24 unified channels

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1 eTPU2 second generation eTPU

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32 standard channels

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1 reaction module 6 channels with 3 outputs per channel

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2 enhanced queued analog-to-digital converters eQADCs

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Forty 12-bit input channels

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688 ns minimum conversion time

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On-chip CAN/SCI Bootstrap loader with Boot Assist Module BAM

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Nexus: Class 3+ for core; Class 1 for eTPU

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JTAG 5-pin

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Development Trigger Semaphore DTS

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Clock generation

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On-chip 4-40 MHz main oscillator

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On-chip FMPLL frequency-modulated phase-locked loop

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Up to 112 general purpose I/O lines

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Power reduction modes: slow, stop, and standby

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Flexible supply scheme

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5 V single supply with external ballast

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Multiple external supply: 5 V, 3.3 V , and 1.2 V

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Designed for LQFP176, LBGA208, PBGA324