PGA117

具有 MUX 的零漂移、可编程增益放大器

The PGA112 and PGA113 devices binary and scope gains offer two analog inputs, a three-pin SPI interface, and software shutdown in a 10-pin, VSSOP package. The PGA116 and binary and scope gains offer 10 analog inputs, a SPI interface with daisy-chain capability, and hardware and software shutdown in a 20-pin TSSOP package.

All versions provide internal calibration channels for system-level calibration. The channels are tied to GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively. VCAL, an external voltage connected to Channel 0, is used as the system calibration reference. Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, 5, 10, 20, 50, 100, and 200.

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Rail-to-Rail Input and Output

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Offset: 25 µV Typical, 100 µV

Maximum

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Zerø Drift: 0.35 µV/°C Typical, 1.2 µV/°C

Maximum

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Low Noise: 12 nV/√Hz

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Input Offset Current: ±5 nA Maximum 25°C

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Gain Error: 0.1% Maximum G ≥ 32,

0.3% Maximum G > 32

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Binary Gains: 1, 2, 4, 8, 16, 32, 64, 128 PGA112,

PGA116

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Scope Gains: 1, 2, 5, 10, 20, 50, 100, 200

PGA113, PGA117

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Gain Switching Time: 200 ns

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2 Channel MUX: PGA112, PGA113

10 Channel MUX: PGA116, PGA117

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Four Internal Calibration Channels

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Amplifier Optimized for Driving CDAC ADCs

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Output Swing: 50 mV to Supply Rails

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AVDD and DVDD for Mixed Voltage Systems

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IQ = 1.1 mA Typical

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Software and Hardware Shutdown: IQ ≤ 4 µA

Typical

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Temperature Range: –40°C to 125°C

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SPI™ Interface 10 MHz With Daisy-Chain

Capability