PIC16C71/JW

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The high performance of the PIC16CXXfamily can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16CXXuses a Harvard architecture, in which, program and data are accessed from separate memories using separate buses. This improves bandwidth over traditional von Neumann architecture in which program and data are fetched from the same memory using the same bus.Separating program and data buses further allows instructions to be sized differentlythan the 8-bit wide data word.Instruction opcodes are 14-bits wide making it possible to have all single word instructions.A 14-bitwide program memory access bus fetches a 14-bitinstruction in a single cycle.A two stage pipeline overlaps fetch and execution of instructions Example 3-1.Consequently, all instructions 35 execute in a single cycle 200 ns@ 20 MHz except for program branches.