MC100EP142FAR2G

3.3 V / 5 V ECL 9位的移位寄存器 3.3 V / 5 V ECL 9-Bit Shift Register

The MC10EP/100EP142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0 - D8 accept parallel input data, while S-IN accepts serial input data. The Qn outputs do not need to be terminated for the shift operation to function. To minimize noise and power, any Q output not used should be left unterminated.The SEL Select input pin is used to switch between the two modes of operation - SHIFT and LOAD. The shift direction is from bit 0 to bit 8. Input data is accepted by the registers a set-up time before the positive going edge of CLK0 or CLK1; shifting is also accomplished on the positive clock edge. A HIGH on the Master Reset pin MR asynchronously resets all the resisters to zero.The 100 Series contains temperature compensation.

Features

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> 3 GHz Minimum Shift Frequency

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9-Bit for Byte-Parity Applications

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Asynchronous Master Reset

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Dual Clocks

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PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V

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NECL Mode Operating Range: VCC = 0 V with VEE = –3.0 V to –5.5 V

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Open Input Default State

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Safety Clamp on Inputs