AD9517-3BCPZ

Clock Generator 48Pin LFCSP EP Tray

Product Details

The AD9517-31 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 1.75 GHz to 2.25 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used.

The AD9517-3 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements.

The AD9517-3 features four LVPECL outputs in two pairs and four LVDS outputs in two pairs. Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.

For applications that require additional outputs, a crystal reference input, zero-delay, or EEPROM for automatic configuration at startup, the AD9520 and AD9522 are available. In addition, the AD9516 and AD9518 are similar to the AD9517 but have a different combination of outputs.

Each pair of outputs has dividers that allow both the divide ratio and coarse delay or phase to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024.

The AD9517-3 is available in a 48-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply VCP to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V nominal.

The AD9517-3 is specified for operation over the industrial range of −40°C to +85°C.

**Applications**

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Low jitter, low phase noise clock distribution

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10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4

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Forward error correction G.710

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Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

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High performance wireless transceivers

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ATE and high performance instrumentation

1 AD9517 is used throughout to refer to all the members of the AD9517 family. However, when AD9517-3 is used, it is referring to that specific member of the AD9517 family.

### Features and Benefits

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**Low phase noise, phase-locked loop PLL

**On-chip VCO tunes from 1.75 GHz to 2.25 GHz

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External VCO/VCXO to 2.4 GHz optional

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1 differential or 2 single-ended reference inputs

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Reference monitoring capability

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**2 pairs of 1.6 GHz LVPECL outputs

**Each output pair shares a 1-to-32 divider with coarse phase delay

Additive output jitter: 225 fs rms

Channel-to-channel skew paired outputs of <10 ps

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**2 pairs of 800 MHz LVDS clock outputs

**Each output pair shares two cascaded 1-to-32 dividers with coarse phase delay

Additive output jitter: 275 fs rms

Fine delay adjust Δt on each LVDS output

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Each LVDS output can be reconfigured as two 250 MHz CMOS outputs

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Automatic synchronization of all outputs on power-up

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See datasheet for additonal features