AD21478WYSWZ2A02

数字信号处理器和控制器 - DSP, DSC 266MHz W/3M Bits RAM LOWER POWER

* Two processing elements PEx, PEy, each of which comprises an ALU, multiplier, shifter, and data register file * Two data address generators DAG1, DAG2 * A program sequencer with instruction cache * PM and DM buses capable of supporting 2 × 64-bit data transfers between memory and the core at every core processor cycle * One periodic interval timer with pinout * On-chip SRAM up to 5M bit * A JTAG test access port for emulation and boundary scan. The JTAG provides software debug through user breakpoints, which allows flexible exception handling.